July 8, 2026

Coyote v2: Raising the Level of Abstraction for Data Center FPGAs

seperate service layer from static layer, reconfigure it dynamically

Topic

FPGA shell optimization

Problem: Integrating FPGA in larger systems is challenging.

Everytime, should start developing from scratch.

So should spend almost 75% effort to build just the infrastructure (networking, I/O, communication w.host)

Can’t reuse the infrastructure

infrastructure is tightly integrated w. app

Prior works: let’s focus on FPGA shells optimization

why?

• FPGA shell provides abstraction & infrastructure to access shared resources.
• FPGA shell can include features: ex) memory virtualization, run-time reconfiguration, or process isolations

Limitation

priorworks

• can’t support complex services, such as networking stacks.
• even they support it, they can’t reconfigure service in runtime.

Why we should reconfigure service?

realworld workloads are dynaimc in nature. ex. switching from TCP/IP to RDMA … etc

Goal & Solution

1. Support commonly used services

ex) memory controllers(HBM), networking stacks (RDMA, TCP/IP), compression & encryption cores, memory virtualization.. etc

Implement service compatibly

ex.) Seamlessly moves data : host CPU <-> FPGA

highly configurable memory management unit

2. Makes service reconfigurable

Solution : seperate the service from static layer, and reconfigure it dynamically.

Effect

1. simplify static layer -> easier to port to other FPGAs
2. independent run-time reconfiguration of both services & user apps -> partial reconfiguration takes much less time than full reconfiguration
3. Can reuse upper layers -> reduce synthesis times

Also need to cover what other priorworks have

3. Spatial sharing with partial reconfiguration of the user region

support

Further Improvement

Improved Pipelining to run application /by Service multiple requests simultaneously

thanks to abstraction

low latency in data movement :by host memory <-> user application

bypassing FPGA HBM

Interface allows user applications to issue DMA requests from HW, (rather than relying on the host software)

Generic interrupt interface

Design

3 layer hardware design

0. shell

reconfigured with config & can be set partially / dynamically. shell is fully parameterized by its services & user apps.

1. static layer

• static layers job is only : provide a link between the host CPU <-> the FPGA
• route the data & control signals -> correct service, user layer
• Main component : device driver

  CPU-FPGA Link

  to handle data & control flow: use XDMA core / can be controlled from both CPU and FPGA => fast and easy to control

• do writeback : update host memory counter when fransfer finishes -> reduce unnecessary PCIe polling -> free up bandwidth

Reconfiguration controller

fully utilize the ICAP bandwidth by loading the bitstream from host memory via PCIe & dedicated XDMA channel.

2. the dynamic (service) layer

Multi-tenant Fair Sharing

• packetization: divide stransferes into chunks -> precise control / efficient saturation of both local & remote links
• round-robin : distributes limited bandwidth links -> fair resource allocation / preserve order

3. the application (user) layer

consist of multiple parallel vFPGAs

Generic App interface

• control bus : memory-mapped for each vFPGA directly into the user space , bypassing the kernel -> lower latency
• interrupt channel
• parallel {host, card, network} interface
• read & write {send, completion} : parallel -> higher performance / compared to CPU control all data transfer = bottleneck

Security

• per-vFPGA MMU: ensuring memory isolation between multiple vFPGAs
• credit system : tackle back pressure & deadlocks

  User-facing, high-level software API

Evaluation

reduces synthesis times between 15% and 20% and run-time reconfiguration times by an order of magnitude, when compared to existing systems.

Thoughts

what is the good problem?

1. It matters
2. It is intellectually interesting
3. Priorwork can’t do this becuase they have inherent limitation.

if something is slow, always look into whether that part is separatable

Inputs

What is FPGA?: Customizable hardware

A field programmable gate array (FPGA) is a flexible integrated circuit that can be reprogrammed after manufacturing to perform custom digital logic functions.

HDL / Hardware Description Language

Describes hardware circuits

Intellectual Property core

a block of logic or data that is used in the creation of a semiconductor chip a reusable HDL component in FPGA, programmable system-on-chip (SoC), and ASIC design

The Memory Management Unit (MMU)

responsible for the translation of virtual addresses used by software to physical addresses used in the memory system.

High Bandwidth Memory (HBM)

type of computer memory that is designed to provide both high-bandwidth and low power consumption

• HBM achieves high bandwidth by having many parallel memory channels, and it achieves lower power consumption by placing the memory close to the processor and reducing the energy needed to move data.

What is card in FPGA?

FPGA boards

DMA: Direct Memory Access

allows hardware components to access the main system memory independently of the CPU.

RDMA : Remote DMA

Network-based DMA, Different machines, ex) Server A RAM ↔ Server B RAM

XDMA/QDMA : Local DMA

Specific DMA hardware IP, Same machine, ex) FPGA ↔ CPU RAM through PCIe

AXI : Advanced eXtensible Interface.

a standard hardware communication interface (protocol) used in FPGA and SoC designs to let different hardware modules communicate with each other.

SRAM == cache , DRAM == memory

Memory striping

splitting data across multiple memory banks/channels so they can work in parallel.